1. Field of the Invention
The present invention relates to pipelined processors. More particularly, this invention relates to means and method for determining whether the pipeline in a processor should be saved while servicing a processor trap.
2. Background of Related Art
Modem processors have incorporated pipelining as a means for increasing the performance of computer systems. Pipelining is an implementation technique wherein multiple instructions are overlapped in execution. A pipelined architecture machine comprises multiple stages. Each stage in the pipeline completes a pan of execution of the instruction. The work of each instruction is broken into smaller portions, each of which takes a fraction of time needed to complete the entire instruction. The stages are connected to each other in order to form a pipe, instructions entering at one end, being processed through each of the stages, and exiting at the other end.
In a pipelined architecture machine, instructions are executed on a piece-meal basis. In order to execute an instruction, it may take several clock cycles for the instruction to complete operation. Each stage of the execution updates various contents of memory and registers in the machine during execution. If an interrupt or a trap occurs during instruction execution, the trap must be serviced, and pipeline execution must be restarted at the place where it was halted. This requires an implementation to restore the pipeline and any registers and/or memory to the state where instruction execution was halted. This must be done because, by the the time the trap is encountered, several other instructions will be in the pipeline at various stages of execution. Therefore, a variety of attempts have been made to preserve the contents of the pipeline in order to service traps or interrupts which occur during execution.
One technique for trap handling involves saving all the contents of the pipeline prior to servicing the trap. A disadvantage of saving the entire pipeline prior to servicing the trap is the overhead resulting from saving of the pipeline. The saving of the entire pipeline prior to servicing the trap requires that the processor use memory to save all the pipes. It also takes some time to save all the pipes. In a high-performance processor which has multiple-stage pipeline, the saving operation may consume significant amounts of memory and several clock cycles of processor execution. In addition to saving the entire pipeline prior to servicing the trap, the pipelines must be restored to their original state prior to resuming operation. This involves fetching each of the memory locations from memory and advancing the pipeline one stage until the pipes are restored to their original state. This process also takes a substantial period of time. The combination of saving and restoring the pipelines for servicing traps thus slows overall performance of the processor.
In some situations, saving the pipeline may not be necessary. For instance, certain architectures support both pipelined instructions as well as so-called "scalar" or non-pipelined instructions. When executing scalar instructions, the contents of the pipeline may not be desired to be saved. Also, some trap handling techniques may not modify the pipes or registers at all. Therefore, in some instances, the resulting overhead from saving and restoring the pipelines prior to trap servicing is not required. No means for distinguishing between instructions which do not require the saving of the processor pipelines for servicing traps is provided in the prior art.